#1 dc offset
Posted: Tue Dec 12, 2017 6:23 pm
Moving on from the disappointment of the F6’ inability to drive the electrostatics….I’m working on a 3 stage AB with lateral fets and minimum idle current requirement. So I updated spice to xvii to make a start.
I tested spice with a jfet buffer (2sk170/2sj74)and tinkered with the models to get the idss to match. I noticed that the buffer output has a distinct DC offset, varying with the idss match.
Anybody got a feel for the effects of an offset in an early stage. Academic in this project because I'm unlikely to use such a buffer here, just curious.
I tested spice with a jfet buffer (2sk170/2sj74)and tinkered with the models to get the idss to match. I noticed that the buffer output has a distinct DC offset, varying with the idss match.
Anybody got a feel for the effects of an offset in an early stage. Academic in this project because I'm unlikely to use such a buffer here, just curious.