dc offset

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ed
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dc offset

Post by ed » Tue Dec 12, 2017 6:23 pm

Moving on from the disappointment of the F6’ inability to drive the electrostatics….I’m working on a 3 stage AB with lateral fets and minimum idle current requirement. So I updated spice to xvii to make a start.

I tested spice with a jfet buffer (2sk170/2sj74)and tinkered with the models to get the idss to match. I noticed that the buffer output has a distinct DC offset, varying with the idss match.

Anybody got a feel for the effects of an offset in an early stage. Academic in this project because I'm unlikely to use such a buffer here, just curious.
buff test.jpg
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IslandPink
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Re: dc offset

Post by IslandPink » Tue Dec 12, 2017 6:42 pm

First I've heard of the F6 problem !
But seriously, interested to know in what way it failed and just thinking about whether you can insert the electrostats as a complex load in Spice and verify where you're going with this new amp ?
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ed
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Re: dc offset

Post by ed » Tue Dec 12, 2017 8:01 pm

see here!, now pay attention I'll be asking the difficult questions shortly.

viewtopic.php?f=9&t=7086

It hasn't failed..it's back in the studio set-up driving ariels.
and verify where you're going with this new amp ?
I'm happy with the tpa3116 for what it's worth but after playing with a couple of budget SS class AB amps, one of which took 13 watts out of the wall, I'm curious to see if I can come up with something. It will make a change from taking 300 watts out of the wall if I pull it off. I'm looking at it in an 'object oriented' kind of way, treating each amp stage as though it were a class in an OO program development.
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Nick
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Re: dc offset

Post by Nick » Tue Dec 12, 2017 8:33 pm

Anybody got a feel for the effects of an offset in an early stage
I would guess it would be entirely dependent on what follows it.
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